This invention relates to analog circuits, and more particularly, to RF analog circuits of the type in which several transistors or other amplifying devices are combined to amplify a RF input signal. More specifically, the invention is directed to a technique for controlling the bias levels of selected amplifying devices in response to a degradation in a supply voltage.
The use of amplifiers and other circuits for signal conditioning radio frequency signals is well known in the art. RF analog circuits have been used in radio transceivers, television receivers, CB radios, microwave links, satellite communications systems, local RF networks, and other wireless communication and broadcast applications. A critical component of many amplifiers is the voltage bias circuitry that is used to bias the internal amplifying devices.
It is known that transistors and other amplifying devices typically have an active region in which there is a substantially linear relationship between gate or grid voltage and drain or plate current. The voltage bias circuitry is typically designed to provide a bias level that, when a null signal is applied to the grid, gate or other control electrode, the output current is at a desired quiescent level in about the center of the linear region of the device""s active region. This bias condition typically provides optimum performance for the amplifier.
It is also desirable to provide a bias level such that a sufficient voltage is maintained across each amplifying device over all operating conditions, so as to avoid device saturation. If critical amplifying devices enter saturation, the amplifier may no longer operate in the linear range.
One important performance characteristic for many amplifiers is the dynamic range of the amplifier. The dynamic range corresponds to the range from the minimum usable input signal to the maximum usable input signal. The minimum usable input signal is often dictated by the internal noise of the amplifier. The maximum usable input signal is the maximum input signal that the amplifier can accept and amplify without distortion. The maximum usable input signal is typically dependent on a number of factors including the supply voltage used and the gain of the amplifier.
For many applications, such as low power applications, it is desirable to use a relatively low supply voltage. Since the dynamic range of an amplifier is typically dependent on the supply voltage, the dynamic range of an amplifier that is powered by a relatively low supply voltage tends to be less than a similar amplifier that is powered by a higher supply voltage.
In addition, it is also desirable to use a self-contained power source such as a battery or the like for many low power applications. The reason some applications are low power applications is because they are powered by a battery. As is known, however, the voltage provided by batteries tends to degrade over time, especially for alkaline batteries. Accordingly, the dynamic range of an amplifier that is powered by a battery will tend to degrade over time. Moreover, if the supply voltage degrades beyond some critical point, some or all of the amplifying devices may enter saturation and the amplifier may cease to operate in a linear mode.
One approach for maintaining the functionality and performance of an amplifier when using a low and/or degrading power supply is to optimize the bias levels under worst case conditions. For example, the bias levels may be set so that after the supply voltage degrades over time, a sufficient voltage is still maintained across each amplifying device to prevent device saturation. A limitation of this approach is, of course, that the performance of the amplifier is typically less than optimal under nominal conditions. Further, the design constraints imposed by designing an amplifier that uses fixed bias levels to maintain satisfactory performance over all operating conditions can increase the complexity of the design.
What would be desirable, therefore, is an amplifier that has a compensation circuit that dynamically compensates selected bias levels within the amplifier to maintain operation and performance over a relatively wide range of supply voltages. This may increase the performance of the amplifier under all operating conditions, and may significantly simplify the amplifier design.
The present invention overcomes many of the disadvantages of the prior art by providing a compensation circuit that dynamically compensates selected bias levels of an operational circuit (e.g., amplifier) in response to variations in the supply voltage. The compensation circuit changes selected bias levels in view of sensed variations in the supply voltage so that the functionality and performance of the operational circuit are substantially maintained.
In one illustrative embodiment, a circuit node is selected within an operational circuit, wherein the voltage at the selected circuit node is dependent on variations in the supply voltage. A comparator is used to compare a reference voltage, which is preferably relatively independent of the variations in the supply voltage, against the voltage sensed at the selected circuit node. A compensation circuit then adjusts selected bias levels in the operational circuit such that the voltage at the selected circuit node becomes equal to (or has some other predetermined relationship with) the reference voltage.
In one embodiment, the operational circuit is an amplifier that has a differential pair of transistors and a current source transistor. The drain of the current source transistor is connected to the source of each of the differential pair of transistors. Each of the drain terminals of the differential pair of transistors is connected to the supply voltage through a corresponding load resistor. A differential output signal is then provided between the drain terminals of the differential pair of transistors. In another embodiment, only one of the two drain terminals is tapped, thus making a single-ended output.
To keep the differential pair of transistors and/or the current source transistor operating in the active region, a sufficient voltage is maintained across each of them. This is preferably accomplished by limiting the maximum current that can pass through each of the load resistors. By doing so, the maximum voltage drop across each of the load resistors is small enough so that the differential pair of transistors and the current source transistor are kept out of saturation.
Preferably, the voltage at a selected node, such as the source terminals of the differential pair of transistors, is monitored. Using an active feedback loop, the bias level provided to the gate terminals of the differential pair of transistors is adjusted so that the current that flows through the load resistors is limited, and the voltage across the load resistor is controlled. Because the voltage drop across the load resistors is limited, a sufficient voltage remains at the source of the differential pair of transistors, which keeps at least the current source transistor out of saturation.
It is contemplated that the active feedback loop may include a comparator, such as an operational amplifier, for comparing the voltage at the source of the differential pair of transistors to a reference voltage. The reference voltage may be set to be substantially greater than or equal to the saturation voltage of the current source transistor.
In another embodiment, the compensation circuit senses the voltage at the drain of either of the differential pair of transistors. Like the previous embodiment, this embodiment adjusts the bias level at the gate terminals of the differential pair of transistors until the voltage at the drain terminal equals a reference voltage. In this embodiment, the reference voltage may be set substantially equal to the saturation voltage of the current source transistor plus the saturation voltage of the differential pair of transistors.
An input stage may be used to adjust the gate terminals of the differential pair of transistors. The input stage may include one or more amplifying devices such as FETs or BJTs connected between ground and the gate terminals of the differential pair of transistors. The one or more amplifying devices may have, for example, a FET connected in series with a cascode transistor. A pull-up resistor may then be connected between the gate terminals of the differential pair of transistors and the supply voltage. The gate of one of the amplifying devices may receive an RF input signal.
In use, when the RF input signal goes high, the drive of the FET or BJT devices of the input stage may increase, allowing a larger current to flow through the pull-up resistor. This causes a larger voltage drop across the pull-up resistor, and a corresponding reduction in voltage at the gate terminals of the differential pair of transistors. Likewise, when the RF input signal goes low, the drive of the FET or BJT devices may decrease, causing a smaller current to flow through the pull-up resistor. This causes a smaller voltage drop across the pull-up resistor, and a corresponding rise in voltage at the gate terminals of the differential pair of transistors. Thus, for RF type signals, the input stage may function as an inverting amplifier.
To help adjust the bias level at the gate terminals of the differential pair of transistors, the input stage may include a current stealing circuit. The current stealing circuit may include, for example, a bypass transistor or the like that is connected in parallel with the pull-up resistor. The gate of the bypass transistor may be controlled by the output of the comparator. As described above, the comparator may include an operational amplifier or the like that compares the voltage of a selected node of the operational circuit, such as the drain (or source) of a differential pair of transistors, to a reference voltage.
If the voltage of the drain (or source) of the differential pair of transistors is higher than a reference voltage, the comparator may decrease the voltage at the gate of the bypass transistor, which provides a bypass current around the pull-up resistor, and increases the bias voltage at the gate terminals of the differential pair of transistors. An increased voltage at the gate terminals of the differential pair of transistors increases the current through the load resistors, and reduces the voltage at the drain (or source) of the differential pair of transistors.
Likewise, if the voltage at the drain (or source) of the differential pair of transistors has a voltage that is lower than the reference voltage, the comparator may increase the voltage at the gate of the bypass transistor, which in turn decreases the bias voltage at the gate terminals of the differential pair of transistors. A decreased voltage at the gate terminals of the differential pair of transistors decreases the current through the load resistors, and increases the voltage at the drain (or source) of the differential pair of transistors. Thus, the bias levels of the differential pair of transistors may be dynamically adjusted so that the amplifier may maintain operation and performance over a relatively wide range of supply voltages.
It is contemplated that the compensation circuit may adjust circuit parameters other than the bias voltage at the gate terminals of a differential pair of transistors, so long as they directly or indirectly cause the voltage at the selected circuit node to assume a predetermined relationship with the reference voltage. For example, in another embodiment of the present invention, the current stealing circuitry is placed in parallel with one or more of the load resistors of the differential amplifier circuit. The current stealing circuitry may include a bypass transistor that selectively bypasses current around one or more of the load resistors to adjust the voltage at the drain terminals of the differential pair of transistors. This approach provides another illustrative way to control the voltage of the drain (or source) terminals of the differential pair of transistors.
In this latter embodiment, bypass transistors are preferably placed in parallel with each of the load resistors. The bypass transistors preferably have gate terminals that are controlled by a comparator, wherein the comparator compares the voltage at a selected circuit node of the operational circuit, such as the drain (or source) of the differential pair of transistors, to a reference voltage. Rather than adjusting the bias level of the gate terminals of the differential pair, however, the bypass transistors of this embodiment adjust the voltage at the source of the differential pair of transistors by providing a controllable resistance in parallel with the load resistors.
In use, if the voltage at the drain (or source) of the differential pair of transistors is higher than a predetermined reference voltage, the comparator increases the voltage at the gate terminals of the bypass transistors. This increases the resistance between the source of the differential pair of transistors and the supply voltage, and for a given source/drain current, decreases the bias level at the drain (or source) of the differential pair of transistors. Likewise, if the voltage at the drain (or source) of the differential pair of transistors is lower than the reference voltage, the comparator decreases the voltage at the gate of the bypass transistors. This decreases the resistance between the source of the differential pair of transistors and the supply voltage, and for a given source/drain current, increases the bias level at the drain (or source) of the differential pair of transistors. What is provided, then, is a compensation circuit that can dynamically compensate selected bias levels within an operational circuit (e.g., amplifier) to maintain operation and performance over a relatively wide range of supply voltages.